Test Center: Intel's Nehalem Simply Sizzles
Comparing Nehalem Xserve to Others

In this review, I evaluate three entry-level systems (one each from Dell, HP, and Lenovo) and two midrange to high-end systems (from HP and Dell). In an ideal world, it would have been fun to allow the vendors to send their biggest, fastest system and throw those up against each other to see what shakes out. However, top-end workstations today can hold 192GB of RAM, which alone can push system costs into the multiple tens of thousands of dollars. So we settled for high-end workstations under $9,000. This left unexplored only the super-high-end market, which is dominated by specialty applications and narrow industry niches.

[ Compare the Dell, HP, and Lenovo workstations on features. Compare their performance benchmark results, power consumption, and scorecards. ]

Why Nehalem matters Intel's Nehalem processors represent a truly new generation in the storied x86 processor history. Their release adds so many new features to the processor family that it appears almost unrecognizable. The key new elements are a built-in memory controller on each chip and high-speed interconnect between processors and peripherals. The interconnect, called QPI (QuickPath Interconnect), replaces the long-maligned FSB (front-side bus) that Intel chips were known for, while providing a superset of its functionality. QPI and on-chip memory controllers are both ideas initially implemented for x86 chips by AMD. In this first release, Intel has clearly refined the implementation. The result of both technologies is consistently greater levels of memory transfer than could be attained previously. (As shown in the accompanying benchmark table, the slowest system we review here has memory bandwidth that's twice that of the fastest system a year ago -- even though memory latency has decreased by only around 20 percent.)

In addition to these advances, Nehalem sports two important changes. First, the cache architecture has been moved to a three-tier system from the previous two tiers. The outermost, Level 3 (L3) cache is a stout 8MB shared by all four cores. When fewer cores are busy, the remaining cores get access to more of the cache. Each core can actually run two threads at once. This SMT (simultaneous multithreading) is a redux of Intel's earlier Hyper-Threading technology, although it scales better on Nehalem than in its original implementation. Hyper-Threading means that eight threads can run at once on a single processor -- that's a lot of instructions in flight at any given moment.