Research at WPI Could Produce a New Class Of Computer Chip

A new research project at Worcester Polytechnic Institute (WPI) is aimed at developing an entirely new type of reconfigurable computing device, one that combines the speed and power efficiency of custom-designed chips with the low cost and flexibility of programmable devices, according to a statement from the university.

The work is being funded by the Defense Advanced Research Projects Agency (DARPA), the central research and development organization for the Department of Defense, which recently granted a Young Faculty Award to Xinming Huang, assistant professor of electrical and computer engineering at WPI. Huang was one of only 10 researchers nationwide to receive a 2007 Young Faculty Award from the agency, whose mission is to fund high-risk research with the potential to dramatically advance traditional military roles and missions, says the university statement.

The 18-month, $150,000 award will support Huang’s effort to close an important technology gap that divides the two primary ways of designing and building chips to run electronic devices.

Most consumer electronics, from cell phones to PDAs to MP3 players, use application-specific integrated circuit (ASIC) chips, which are “hard-wired” to perform specific jobs and cannot be reprogrammed. Field-programmable gate arrays (FPGAs), on the other hand, contain a general-purpose array of components that can be reprogrammed on the fly to do different tasks.

Each technology has advantages and disadvantages. ASICs are more power efficient than FPGAs, which, because they are designed to be universal, have many redundant electronic components, all of which consume power whether or not they are needed to carry out a particular application. Because they are programmed by software, rather than having their functions hard-wired into silicon, FPGAs cost a small fraction of the $1 million to $2 million it takes to design a new ASIC chip, explains the WPI statement.

Huang’s reconfigurable computing device, called the smart cell, will combine the advantages of ASICs and FPGAs. It will incorporate more than a thousand individual processors wired onto a silicon substrate. Each processor will be responsible for performing a single operation, such as addition or multiplication, as data flows through the chip. Using a type of parallel computing called stream processing, the chip will complete hundreds of calculations simultaneously, enabling it to perform up to 300 times faster than microprocessors and about 15 times faster than FPGAs.

—Esther Schindler

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