As Intel and Advanced Micro Devices (AMD) race toward smaller, faster chips, the fierce competition is taking its toll as both companies struggle to maintain profit margins by using more efficient manufacturing.
At the tiny scale of 45-nanometer transistors and wires, a single speck of dust on a 300-millimeter silicon wafer can destroy an entire processor. Lower manufacturing yields cut into a company’s profit margin, reducing the number of functional chips they can sell from each wafer.
“As an industry, we’re running out of gas at 45-nanometer geometry,” said Nick Kepler, vice president of logic technology development for AMD. “We’ve been unable to scale the size as much as we used to because of leakage. We’re still putting transistors closer together, but not shrinking the gates. So geometry shrinks can hurt you now, which they haven’t in the past.”
One problem is that 65-nanometer and 45-nanometer chip components have shrunk so far that they are now smaller than the wavelength of the light used to carve those features onto silicon chips. To fight that trend, AMD and IBM said Tuesday they will use three new technologies to boost manufacturing efficiency.
By the second half of 2008, AMD expects to be producing 45-nanometer chips using immersion lithography, ultra-low-k interconnect dielectrics and enhanced transistor strain. The companies made the announcement at the International Electron Device Meeting in San Francisco.
By inserting liquid instead of air between the projection lens and the wafer, AMD and IBM can reduce the wavelength of the light, giving them a 40 percent gain in resolution compared to dry lithography and allowing them to sell a higher percentage of the hundreds of chips on every wafer, Kepler said.
Likewise, IBM plans to produce 65-nanometer server chips by the second half of 2007, then shrink both server and gaming chips to 45 nanometers at some point in the future, said Gary Patton, vice president of technology development for IBM’s semiconductor research and development center. AMD and IBM have cooperated on chip development since 2003, and last year extended their contract through 2011 to reach the 32-nanometer and 22-nanometer chip generations.
In response, Intel says that it beat AMD to the market with 65-nanometer chip sales by more than a year, and has already begun producing samples of its 45-nanometer “Penryn” quad-core chip for notebooks, desktops and servers. Intel plans to ship those chips in the second half of 2007.
Even if AMD improves its manufacturing, Intel is poised to continue its lead in shrinking chip geometries because it has shorter gate lengths and static RAM (SRAM) cell sizes, said Rob Willoner, a technology analyst with Intel’s technology and manufacturing group.
“People have different meanings when they talk about the 65-nanometer process. There’s not an industry standard,” he said. AMD’s Opteron chip was a commercial success because its excellent design compensated for poor dimensions at the 90-nanometer scale, he said.
Chips with a greater cache of local memory stored in SRAM cells can avoid the time-intensive process of retrieving data from external sources. At the same conference in San Francisco this week, Intel announced plans to use “floating-body cells” to further increase the amount of on-chip memory, according to published reports.
Despite the manufacturing challenges, chip companies continue to build smaller features because of the tremendous performance benefits. By shrinking from 90 to 65 nanometers, Intel chips have double the transistor density while reducing leakage fivefold (at constant performance) and requiring 30 percent less switching power.
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